1. Field of the Invention
The present invention relates, in general, to interconnect structures for integrated circuits, and, more particularly, to a contact structure manufactured with fewer mask steps for random access memory circuits.
2. State of the Art
Integrated circuits are mass produced by fabricating hundreds of identical circuit patterns on a single semiconductor substrate. The fabricated wafer is sawed into hundreds of identical dies or chips. While integrated circuits are commonly referred to as "semiconductor devices" they are in fact fabricated from various materials including conductors, insulators, and semiconductors. Silicon, the most commonly used semiconductor material, can be used in either the single crystal or polycrystalline form. In the integrated circuit fabrication art, polycrystalline silicon is usually called "polysilicon" or simply "poly".
MOS (Metal Oxide Semiconductor) technology is currently the most commonly used integrated circuit technology, and thus the present invention will be described in terms of silicon-based MOS technology, although it is evident that it will find uses in other integrated circuit technologies.
MOS integrated circuit fabrication uses a lightly-doped silicon substrate or lightly-doped epitaxial silicon (deposited crystalline silicon) on a heavily doped substrate. Devices are formed in and on the substrate using many available processing techniques. An area in an integrated circuit in which electrical devices are formed is generally called an active area. The active areas on a chip are covered with a protective insulating layer. Conductive structures called "contacts" extend through the protective insulating layer to electrically couple to the active areas.
The advantages of building integrated circuits with smaller individual circuit elements so that more and more circuitry may be packed on a single chip are well-known: electronic equipment becomes less bulky, reliability is improved, assembly and packaging costs are minimized, and improved circuit functionality and performance, in particular higher clock speeds. However, the smaller the size, the more difficult it is to fabricate and locate individual structures, such as contacts, within the specifications and tolerances required.
As more devices are formed on a single chip, the need for interconnections among the devices increases dramatically. Many circuits require multiple layers of patterned conductive "wiring" to provide these interconnections. Where one patterned conductive layer must couple to another patterned conductive layer or to devices in the substrate, a contact is used to physically and electrically access the lower conductive layer. Because of the large number of contacts it is desirable to minimize the size of each contact.
Recently, a memory cell design has been invented that uses sidewall spacer technology to form a small-dimension contacts to active areas through an insulating layer formed over the active areas. These contacts resemble a vertical column having a lower termination at the active area and a wider termination at the top to ease electrical contact to overlying metallization. This technology is described in U.S. patent application Ser. No. 08/622,591, entitled SEMICONDUCTOR PROCESSING METHOD OF FORMING A CONTACT PEDESTAL, OF FORMING A STORAGE NODE OF A CAPACITOR, AND INTEGRATED CIRCUITRY, assigned to the assignee of the present invention. This technology uses a hardmask to protect the insulating layer during contact etch process. The hardmask deposition adds an extra step of processing. Also, the hardmask must be patterned, adding additional etch processing, and removed once the contact is formed. It is desirable to provide the advantages of the sidewall aligned contact without the use of a hardmask.
It is a significant advantage if an IC design can eliminate one or more processing steps. In particular, it is desirable to eliminate patterning steps that involve multiple steps and add significant cycle time and cost to an integrated circuit process.